libs/kaptan-stm32f7: add clock GPIO and timer drivers

libs/kaptan-stm32f7/src/stm32f722/clock.rs

@@ -0,0 +1,54 @@
+//! Deterministic STM32F722 clock-source selection.
+
+use stm32f7::stm32f722;
+
+const CLOCK_SWITCH_POLL_LIMIT: u16 = 1_024;
+
+/// Failure to establish the board's HSI16 clock profile.
+#[derive(Clone, Copy, Debug, Eq, PartialEq)]
+pub enum ClockProfileError {
+    /// HSI did not become ready within the bounded polling budget.
+    HsiNotReady,
+    /// The system clock did not switch to HSI within the bounded polling budget.
+    SystemClockNotHsi,
+}
+
+/// Selects 16 MHz HSI as SYSCLK with undivided AHB, APB1, and APB2 clocks.
+///
+/// This profile is deliberately selected even when an earlier boot stage left
+/// the device running from a PLL. It establishes the clock assumptions used by
+/// DWT timestamps, USART1 baud calculation, and TIM2 heartbeat scheduling.
+pub fn select_hsi16_profile(rcc: &stm32f722::RCC) -> Result<(), ClockProfileError> {
+    rcc.cr().modify(|_, write| write.hsion().on());
+    if !wait_for_hsi(rcc) {
+        return Err(ClockProfileError::HsiNotReady);
+    }
+
+    rcc.cfgr()
+        .modify(|_, write| write.sw().hsi().hpre().div1().ppre1().div1().ppre2().div1());
+    if !wait_for_system_clock_hsi(rcc) {
+        return Err(ClockProfileError::SystemClockNotHsi);
+    }
+
+    Ok(())
+}
+
+fn wait_for_hsi(rcc: &stm32f722::RCC) -> bool {
+    for _ in 0..CLOCK_SWITCH_POLL_LIMIT {
+        if rcc.cr().read().hsirdy().is_ready() {
+            return true;
+        }
+    }
+
+    false
+}
+
+fn wait_for_system_clock_hsi(rcc: &stm32f722::RCC) -> bool {
+    for _ in 0..CLOCK_SWITCH_POLL_LIMIT {
+        if rcc.cfgr().read().sws().is_hsi() {
+            return true;
+        }
+    }
+
+    false
+}