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refactor(firmware): centralize configuration and diagnostics

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This commit is contained in:
Onur Özkan committed 2026-08-22 18:37:18 +03:00
1 parent 7048ed89d0
commit 387fdaad23
140 files changed
+6891 -4541
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firmware/platforms/stm32f7/src/f722/data_channel.rs
+20 -96
View File
@@ -1,17 +1,17 @@
//! F722 transport and vertical-route adapters for the portable data channel.
use super::{VerticalRoute, peripherals};
use kaptan_data_channel::{DmaCompletion, FrameAdmission, FrameSink, TxHealth, VerticalDataConfig};
use kaptan_data_channel::{FrameSink, VerticalDataConfig};
use kaptan_dma::TxCompletion;
use kaptan_mavlink::{
MavlinkFrame,
encoder::DistanceSensorConfig,
transmitter::{FrameClass, MavlinkTransmitter, TransmitFaultKind},
transmitter::{EnqueueResult, FrameClass, MavlinkTransmitter},
};
// Board endpoint, baud, sensor topology, and mounting remain immutable
// build-time policy. They are not ground-station-editable in this telemetry
// image: the F722 has no authenticated config ingress or activation runtime.
// Baud, sensor topology, and mounting remain immutable build-time policy. The
// output-inhibited board image may recover endpoint identity and selected
// operational rates before this channel is constructed.
pub(crate) const UART1_CLOCK_HZ: u32 = 108_000_000;
pub(crate) const UART2_CLOCK_HZ: u32 = 54_000_000;
pub(crate) const SERVICE_HZ: usize = 100;
@@ -23,7 +23,7 @@ pub(crate) const SERVICE_TIMER_CONFIG: peripherals::Tim2PeriodicConfig =
auto_reload: 99,
};
/// Maps a selected vertical electrical route to development data-channel metadata.
/// Maps a selected vertical electrical route to configured data-channel metadata.
///
/// The values are telemetry descriptions only; they neither calibrate a flight
/// estimator nor authorize an `ExternalControlOnly` profile.
@@ -62,11 +62,9 @@ enum F722MavlinkTransport {
Usart2(MavlinkTransmitter<peripherals::DcacheDisabledDmaMemory, peripherals::Usart2TxDma, 4>),
}
/// Sole F722 MAVLink DMA owner plus unconfigurable transport-loss accounting.
/// Sole F722 MAVLink DMA owner.
pub(crate) struct F722MavlinkTransmitter {
inner: F722MavlinkTransport,
health: TxHealth,
pending_faults: u8,
}
impl F722MavlinkTransmitter {
@@ -85,8 +83,6 @@ impl F722MavlinkTransmitter {
memory,
peripherals::Usart1TxDma::new(rcc, uart),
)),
health: TxHealth::default(),
pending_faults: 0,
})
}
@@ -104,107 +100,35 @@ impl F722MavlinkTransmitter {
memory,
peripherals::Usart2TxDma::new(rcc, uart),
)),
health: TxHealth::default(),
pending_faults: 0,
})
}
}
impl FrameSink for F722MavlinkTransmitter {
fn send(&mut self, class: FrameClass, frame: MavlinkFrame) -> FrameAdmission {
let (admission, start_fault) = match &mut self.inner {
fn send(&mut self, class: FrameClass, frame: MavlinkFrame) -> EnqueueResult {
match &mut self.inner {
F722MavlinkTransport::Usart1(transmitter) => {
let outcome = transmitter.admit_and_start(class, frame);
(
outcome.admission,
outcome.start.err().map(|fault| fault.kind()),
)
let _ = outcome.start;
outcome.admission
}
F722MavlinkTransport::Usart2(transmitter) => {
let outcome = transmitter.admit_and_start(class, frame);
(
outcome.admission,
outcome.start.err().map(|fault| fault.kind()),
)
let _ = outcome.start;
outcome.admission
}
};
if !matches!(
admission,
kaptan_mavlink::transmitter::EnqueueResult::Enqueued
) {
self.health.admission_loss_count = self.health.admission_loss_count.saturating_add(1);
}
if let Some(fault) = start_fault {
self.record_fault(fault);
}
FrameAdmission::Retained(admission)
}
fn on_dma_complete(&mut self, completion: TxCompletion) -> DmaCompletion {
let start_fault = match &mut self.inner {
F722MavlinkTransport::Usart1(transmitter) => transmitter
.on_dma_complete(completion)
.err()
.map(|error| error.kind()),
F722MavlinkTransport::Usart2(transmitter) => transmitter
.on_dma_complete(completion)
.err()
.map(|error| error.kind()),
};
let terminal = matches!(
completion,
TxCompletion::TransferFault | TxCompletion::Halted
);
if let Some(fault) = start_fault {
self.record_fault(fault);
}
if terminal {
self.record_fault(TransmitFaultKind::Terminal);
}
if start_fault.is_some() || terminal {
DmaCompletion::Fault
} else {
DmaCompletion::Complete
}
}
fn health(&self) -> TxHealth {
self.health
}
fn take_transport_fault(&mut self) -> Option<TransmitFaultKind> {
let (bit, fault) = if self.pending_faults & 1 != 0 {
(1, TransmitFaultKind::Memory)
} else if self.pending_faults & 2 != 0 {
(2, TransmitFaultKind::Engine)
} else if self.pending_faults & 4 != 0 {
(4, TransmitFaultKind::Terminal)
} else {
return None;
};
self.pending_faults &= !bit;
Some(fault)
}
}
impl F722MavlinkTransmitter {
fn record_fault(&mut self, fault: TransmitFaultKind) {
self.health.dma_fault_count = self.health.dma_fault_count.saturating_add(1);
self.pending_faults |= match fault {
TransmitFaultKind::Memory => {
self.health.memory_fault_count = self.health.memory_fault_count.saturating_add(1);
1
fn on_dma_complete(&mut self, completion: TxCompletion) {
match &mut self.inner {
F722MavlinkTransport::Usart1(transmitter) => {
let _ = transmitter.on_dma_complete(completion);
}
TransmitFaultKind::Engine => {
self.health.engine_fault_count = self.health.engine_fault_count.saturating_add(1);
2
F722MavlinkTransport::Usart2(transmitter) => {
let _ = transmitter.on_dma_complete(completion);
}
TransmitFaultKind::Terminal => {
self.health.terminal_fault_count =
self.health.terminal_fault_count.saturating_add(1);
4
}
};
}
}
}