refactor(firmware): centralize configuration and diagnostics

firmware/platforms/stm32f7/src/f722/motor_inhibit.rs

@@ -7,8 +7,13 @@
 use stm32f7::stm32f722;
 
 /// Drives PB0/PB1/PB4/PB5 low before selecting push-pull GPIO output mode.
-pub(crate) fn inhibit_motor_pins(rcc: &stm32f722::RCC, port: &stm32f722::GPIOB) {
+pub(crate) fn inhibit_pb0_pb1_pb4_pb5(rcc: &stm32f722::RCC, port: &stm32f722::GPIOB) {
     rcc.ahb1enr().modify(|_, write| write.gpioben().set_bit());
+    // RM0431 section 5.2.12 requires two peripheral clock cycles before the
+    // first access. The volatile enable-register read supplies the standard
+    // synchronization delay and prevents the GPIO write from being reordered
+    // ahead of the clock enable.
+    let _ = rcc.ahb1enr().read().gpioben().bit_is_set();
     port.bsrr().write(|write| {
         write
             .br0()