From 59b604fdba2426abc0fbc8489fd3131b45c8de06 Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Onur=20=C3=96zkan?= <work@onurozkan.dev>
Date: Sat, 1 Aug 2026 22:28:06 +0300
Subject: [PATCH] platforms/stm32f7: keep USART2 DMA requests enabled

---
 .../src/f722/peripherals/usart2_tx_dma1_stream6.rs  | 13 +------------
 1 file changed, 1 insertion(+), 12 deletions(-)

diff --git a/platforms/stm32f7/src/f722/peripherals/usart2_tx_dma1_stream6.rs b/platforms/stm32f7/src/f722/peripherals/usart2_tx_dma1_stream6.rs
index ceb4922..e14abd1 100644
--- a/platforms/stm32f7/src/f722/peripherals/usart2_tx_dma1_stream6.rs
+++ b/platforms/stm32f7/src/f722/peripherals/usart2_tx_dma1_stream6.rs
@@ -27,6 +27,7 @@ impl Usart2TxDma {
     /// Enables DMA1 and connects USART2 TX to its fixed request route.
     pub fn new(rcc: &stm32f722::RCC, usart: Usart2Tx) -> Self {
         rcc.ahb1enr().modify(|_, write| write.dma1en().set_bit());
+        usart.enable_dma_transmit();
         Self { usart }
     }
 
@@ -44,12 +45,8 @@ impl Usart2TxDma {
         }
 
         self.clear_interrupt_flags();
-        // Idle USART2 has TXE set. Enabling DMAT *after* the stream is armed
-        // creates the initial request for byte zero without manually writing
-        // TDR, so the whole frame is owned by DMA.
         self.configure_stream(bytes);
         self.stream().cr().modify(|_, write| write.en().enabled());
-        self.usart.enable_dma_transmit();
         Ok(())
     }
 
@@ -73,14 +70,6 @@ impl Usart2TxDma {
             .st(6)
             .cr()
             .modify(|_, write| write.en().disabled());
-        // SAFETY: USART2 is initialized once by `Usart2Tx::new`; this ISR
-        // clears only its DMA transmit-request enable after the stream's
-        // terminal status has been observed.
-        unsafe {
-            (&*stm32f722::USART2::ptr())
-                .cr3()
-                .modify(|_, write| write.dmat().clear_bit())
-        };
         controller.hifcr().write(|write| {
             write
                 .ctcif6()