build(f722): centralize linker layout

firmware/platforms/stm32f7/link/f722/memory.x

@@ -0,0 +1,33 @@
+MEMORY
+{
+  /*
+   * STM32F72xx flash sectors 0-5 form the 256 KiB application region.
+   * Sectors 6 and 7 are two independently erasable 128 KiB configuration
+   * journal slots at 0x0804_0000 and 0x0806_0000. They are deliberately not
+   * linker regions, so application sections cannot overlap persistent data.
+   */
+  FLASH : ORIGIN = 0x08000000, LENGTH = 256K
+
+  /*
+   * STM32F722 RAM totals 256 KiB:
+   *  - DTCM:  64 KiB at 0x2000_0000
+   *  - SRAM1: 176 KiB at 0x2001_0000
+   *  - SRAM2: 16 KiB at 0x2003_C000
+   *
+   * SRAM1 and SRAM2 are contiguous and DMA-accessible. DTCM remains separate
+   * for a future explicit placement policy.
+   */
+  RAM : ORIGIN = 0x20010000, LENGTH = 192K
+}
+
+/* Absolute symbols are the single source of truth for the Rust NOR adapter. */
+__kaptan_config_slot0_start = 0x08040000;
+__kaptan_config_slot1_start = 0x08060000;
+__kaptan_config_journal_end = 0x08080000;
+
+ASSERT(ORIGIN(FLASH) + LENGTH(FLASH) == __kaptan_config_slot0_start,
+       "application FLASH must end at configuration slot 0")
+ASSERT(__kaptan_config_slot1_start - __kaptan_config_slot0_start == 128K,
+       "configuration slot 0 must be one F722 128 KiB sector")
+ASSERT(__kaptan_config_journal_end - __kaptan_config_slot1_start == 128K,
+       "configuration slot 1 must be one F722 128 KiB sector")