refactor: move firmware workspace under firmware

firmware/platforms/stm32f7/src/f722/motor_inhibit.rs

@@ -0,0 +1,67 @@
+//! Common former-motor-pin interlock for every F722 image.
+//!
+//! This is intentionally independent of profile initialization and is called
+//! as the first PAC access. The GPIO-low interlock is a separate electrical
+//! boundary from all telemetry initialization.
+
+use stm32f7::stm32f722;
+
+/// Drives PB0/PB1/PB4/PB5 low before selecting push-pull GPIO output mode.
+pub(crate) fn inhibit_motor_pins(rcc: &stm32f722::RCC, port: &stm32f722::GPIOB) {
+    rcc.ahb1enr().modify(|_, write| write.gpioben().set_bit());
+    port.bsrr().write(|write| {
+        write
+            .br0()
+            .set_bit()
+            .br1()
+            .set_bit()
+            .br4()
+            .set_bit()
+            .br5()
+            .set_bit()
+    });
+    port.otyper().modify(|_, write| {
+        write
+            .ot0()
+            .push_pull()
+            .ot1()
+            .push_pull()
+            .ot4()
+            .push_pull()
+            .ot5()
+            .push_pull()
+    });
+    port.ospeedr().modify(|_, write| {
+        write
+            .ospeedr0()
+            .low_speed()
+            .ospeedr1()
+            .low_speed()
+            .ospeedr4()
+            .low_speed()
+            .ospeedr5()
+            .low_speed()
+    });
+    port.pupdr().modify(|_, write| {
+        write
+            .pupdr0()
+            .floating()
+            .pupdr1()
+            .floating()
+            .pupdr4()
+            .floating()
+            .pupdr5()
+            .floating()
+    });
+    port.moder().modify(|_, write| {
+        write
+            .moder0()
+            .output()
+            .moder1()
+            .output()
+            .moder4()
+            .output()
+            .moder5()
+            .output()
+    });
+}