refactor(firmware): simplify configuration and diagnostics

firmware/platforms/stm32f7/src/f722/peripherals/clock.rs

@@ -1,6 +1,6 @@
 //! Deterministic STM32F722 PLL clock-source selection.
 
-use kaptan_log::KaptanError;
+use kaptan_err_propagate::KaptanError;
 use stm32f7::stm32f722;
 
 const CLOCK_SWITCH_POLL_LIMIT: u16 = 1_024;
@@ -8,12 +8,19 @@ const CLOCK_SWITCH_POLL_LIMIT: u16 = 1_024;
 /// Failure to establish the 216 MHz PLL clock profile.
 #[derive(Clone, Copy, Debug, Eq, PartialEq, KaptanError)]
 pub enum ClockProfileError {
+    #[kaptan_error(id = 11001)]
     HsiNotReady,
+    #[kaptan_error(id = 11002)]
     SystemClockNotHsi,
+    #[kaptan_error(id = 11003)]
     PllNotStopped,
+    #[kaptan_error(id = 11004)]
     PllNotReady,
+    #[kaptan_error(id = 11005)]
     OverDriveNotReady,
+    #[kaptan_error(id = 11006)]
     OverDriveSwitchNotReady,
+    #[kaptan_error(id = 11007)]
     SystemClockNotPll,
 }