54 lines
1.8 KiB
Rust
54 lines
1.8 KiB
Rust
//! STM32F722 TIM2 periodic interrupt configuration.
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use stm32f7::stm32f722;
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/// Precomputed TIM2 periodic-update configuration.
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#[derive(Clone, Copy, Debug, Eq, PartialEq)]
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pub struct Tim2PeriodicConfig {
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/// Timer prescaler register value.
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pub prescaler: u16,
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/// Timer auto-reload register value.
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pub auto_reload: u32,
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}
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/// TIM2 configured to issue periodic update interrupts.
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pub struct Tim2Periodic {
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peripheral: stm32f722::TIM2,
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}
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impl Tim2Periodic {
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/// Enables TIM2 with the supplied board-derived period configuration.
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pub fn new(
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rcc: &stm32f722::RCC,
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peripheral: stm32f722::TIM2,
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config: Tim2PeriodicConfig,
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) -> Self {
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rcc.apb1rstr().modify(|_, write| write.tim2rst().set_bit());
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rcc.apb1rstr()
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.modify(|_, write| write.tim2rst().clear_bit());
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rcc.apb1enr().modify(|_, write| write.tim2en().set_bit());
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peripheral.cr1().modify(|_, write| write.cen().clear_bit());
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peripheral.psc().write(|write| {
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// SAFETY: `prescaler` is exactly the 16-bit PSC register width.
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unsafe { write.psc().bits(config.prescaler) }
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});
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peripheral.arr().write(|write| {
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// SAFETY: TIM2 ARR is a 32-bit register and accepts `auto_reload`.
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unsafe { write.arr().bits(config.auto_reload) }
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});
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peripheral.egr().write(|write| write.ug().set_bit());
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peripheral.sr().modify(|_, write| write.uif().clear_bit());
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peripheral.dier().modify(|_, write| write.uie().set_bit());
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peripheral.cr1().modify(|_, write| write.cen().set_bit());
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Self { peripheral }
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}
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/// Acknowledges a TIM2 update interrupt.
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pub fn acknowledge_update(&mut self) {
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self.peripheral
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.sr()
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.modify(|_, write| write.uif().clear_bit());
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}
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}
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