90 lines
3.0 KiB
Rust
90 lines
3.0 KiB
Rust
//! Deterministic STM32F722 PLL clock-source selection.
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use stm32f7::stm32f722;
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const CLOCK_SWITCH_POLL_LIMIT: u16 = 1_024;
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/// Failure to establish the 216 MHz PLL clock profile.
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#[derive(Clone, Copy, Debug, Eq, PartialEq)]
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pub enum ClockProfileError {
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HsiNotReady,
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SystemClockNotHsi,
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PllNotStopped,
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PllNotReady,
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OverDriveNotReady,
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OverDriveSwitchNotReady,
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SystemClockNotPll,
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}
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/// Selects the board's HSI PLL profile.
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///
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/// SYSCLK/HCLK run at 216 MHz; APB1 is 54 MHz (timers run at 108 MHz), and
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/// APB2 is 108 MHz. HSI is the PLL source, so no external-crystal assumption
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/// is introduced.
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pub fn select_pll216_profile(
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rcc: &stm32f722::RCC,
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pwr: &stm32f722::PWR,
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flash: &stm32f722::FLASH,
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) -> Result<(), ClockProfileError> {
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rcc.cr().modify(|_, write| write.hsion().on());
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if !wait_until(|| rcc.cr().read().hsirdy().is_ready()) {
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return Err(ClockProfileError::HsiNotReady);
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}
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// Return to HSI before changing a PLL left configured by an earlier boot stage.
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rcc.cfgr().modify(|_, write| write.sw().hsi());
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if !wait_until(|| rcc.cfgr().read().sws().is_hsi()) {
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return Err(ClockProfileError::SystemClockNotHsi);
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}
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rcc.cr().modify(|_, write| write.pllon().off());
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if !wait_until(|| !rcc.cr().read().pllrdy().is_ready()) {
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return Err(ClockProfileError::PllNotStopped);
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}
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// Scale 1, over-drive and seven flash wait states are required at 216 MHz.
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rcc.apb1enr().modify(|_, write| write.pwren().set_bit());
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pwr.cr1().modify(|read, write| unsafe {
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write.bits((read.bits() & !(0b11 << 14)) | (0b11 << 14) | (1 << 16))
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});
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if !wait_until(|| pwr.csr1().read().odrdy().bit_is_set()) {
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return Err(ClockProfileError::OverDriveNotReady);
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}
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pwr.cr1().modify(|_, write| write.odswen().set_bit());
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if !wait_until(|| pwr.csr1().read().odswrdy().bit_is_set()) {
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return Err(ClockProfileError::OverDriveSwitchNotReady);
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}
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flash.acr().modify(|read, write| unsafe {
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write.bits((read.bits() & !0x0f) | 7 | (1 << 8) | (1 << 9))
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});
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// HSI / 16 * 432 / 2 = 216 MHz; Q=9 supplies a 48 MHz domain.
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rcc.pllcfgr()
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.write(|write| unsafe { write.bits(16 | (432 << 6) | (9 << 24)) });
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rcc.cr().modify(|_, write| write.pllon().on());
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if !wait_until(|| rcc.cr().read().pllrdy().is_ready()) {
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return Err(ClockProfileError::PllNotReady);
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}
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rcc.cfgr().modify(|read, write| unsafe {
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// AHB /1, APB1 /4, APB2 /2, SYSCLK = PLL.
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write.bits(
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(read.bits() & !((0x0f << 4) | (0x07 << 10) | (0x07 << 13) | 0x03))
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| (0b101 << 10)
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| (0b100 << 13)
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| 0b10,
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)
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});
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if !wait_until(|| rcc.cfgr().read().sws().is_pll()) {
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return Err(ClockProfileError::SystemClockNotPll);
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}
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Ok(())
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}
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fn wait_until(mut ready: impl FnMut() -> bool) -> bool {
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for _ in 0..CLOCK_SWITCH_POLL_LIMIT {
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if ready() {
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return true;
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}
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}
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false
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}
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