132 lines
4.8 KiB
Rust
132 lines
4.8 KiB
Rust
//! Deterministic STM32F722 PLL clock-source selection.
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use kaptan_err_reportable::KaptanError;
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use stm32f7::stm32f722;
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const CLOCK_SWITCH_POLL_LIMIT: u32 = 1_024;
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// Crystal startup is slower than a clock-tree state transition. This remains
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// bounded so an absent oscillator reaches safe-idle instead of hanging boot.
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const HSE_STARTUP_POLL_LIMIT: u32 = 1_000_000;
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/// Failure to establish the 216 MHz PLL clock profile.
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#[derive(Clone, Copy, Debug, Eq, PartialEq, KaptanError)]
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pub enum ClockProfileError {
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#[kaptan_error(id = 11001)]
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HsiNotReady,
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#[kaptan_error(id = 11002)]
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SystemClockNotHsi,
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#[kaptan_error(id = 11003)]
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PllNotStopped,
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#[kaptan_error(id = 11004)]
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PllNotReady,
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#[kaptan_error(id = 11005)]
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OverDriveNotReady,
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#[kaptan_error(id = 11006)]
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OverDriveSwitchNotReady,
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#[kaptan_error(id = 11007)]
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SystemClockNotPll,
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#[kaptan_error(id = 11008)]
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HseNotReady,
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}
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/// Selects the F722 platform's 8 MHz HSE PLL profile.
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///
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/// SYSCLK/HCLK run at 216 MHz; APB1 is 54 MHz (timers run at 108 MHz), and
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/// APB2 is 108 MHz. Both supported flight-controller boards have an 8 MHz
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/// external oscillator; using it as the PLL source gives USB an accurate
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/// 48 MHz clock through PLLQ.
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pub fn select_pll216_profile(
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rcc: &stm32f722::RCC,
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pwr: &stm32f722::PWR,
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flash: &stm32f722::FLASH,
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) -> Result<(), ClockProfileError> {
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rcc.cr().modify(|_, write| write.hsion().on());
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if !wait_until(CLOCK_SWITCH_POLL_LIMIT, || {
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rcc.cr().read().hsirdy().is_ready()
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}) {
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return Err(ClockProfileError::HsiNotReady);
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}
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// Return to HSI before changing a PLL left configured by an earlier boot stage.
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rcc.cfgr().modify(|_, write| write.sw().hsi());
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if !wait_until(CLOCK_SWITCH_POLL_LIMIT, || rcc.cfgr().read().sws().is_hsi()) {
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return Err(ClockProfileError::SystemClockNotHsi);
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}
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rcc.cr().modify(|_, write| write.hseon().on());
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if !wait_until(HSE_STARTUP_POLL_LIMIT, || {
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rcc.cr().read().hserdy().is_ready()
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}) {
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return Err(ClockProfileError::HseNotReady);
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}
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rcc.cr().modify(|_, write| write.pllon().off());
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if !wait_until(CLOCK_SWITCH_POLL_LIMIT, || {
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!rcc.cr().read().pllrdy().is_ready()
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}) {
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return Err(ClockProfileError::PllNotStopped);
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}
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// Scale 1, over-drive and seven flash wait states are required at 216 MHz.
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rcc.apb1enr().modify(|_, write| write.pwren().set_bit());
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pwr.cr1().modify(|read, write| {
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// SAFETY: this read-modify-write changes only the documented voltage-scale and
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// over-drive-enable fields; it preserves every other PWR_CR1 bit owned by boot.
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unsafe { write.bits((read.bits() & !(0b11 << 14)) | (0b11 << 14) | (1 << 16)) }
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});
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if !wait_until(CLOCK_SWITCH_POLL_LIMIT, || {
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pwr.csr1().read().odrdy().bit_is_set()
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}) {
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return Err(ClockProfileError::OverDriveNotReady);
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}
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pwr.cr1().modify(|_, write| write.odswen().set_bit());
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if !wait_until(CLOCK_SWITCH_POLL_LIMIT, || {
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pwr.csr1().read().odswrdy().bit_is_set()
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}) {
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return Err(ClockProfileError::OverDriveSwitchNotReady);
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}
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flash.acr().modify(|read, write| {
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// SAFETY: these are the STM32F7-documented latency, instruction-cache and
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// data-cache fields for 216 MHz; the read-modify-write retains other ACR bits.
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unsafe { write.bits((read.bits() & !0x0f) | 7 | (1 << 8) | (1 << 9)) }
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});
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// HSE / 8 * 432 / 2 = 216 MHz; Q=9 supplies the exact 48 MHz USB domain.
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rcc.pllcfgr().write(|write| {
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// SAFETY: M=8, N=432, P=/2 (the reset encoding), Q=9, and the HSE source
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// are valid for the 8 MHz board oscillator; the PLL is disabled first.
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unsafe { write.bits(8 | (432 << 6) | (1 << 22) | (9 << 24)) }
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});
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rcc.cr().modify(|_, write| write.pllon().on());
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if !wait_until(CLOCK_SWITCH_POLL_LIMIT, || {
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rcc.cr().read().pllrdy().is_ready()
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}) {
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return Err(ClockProfileError::PllNotReady);
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}
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rcc.cfgr().modify(|read, write| {
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// AHB /1, APB1 /4, APB2 /2, SYSCLK = PLL.
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// SAFETY: this preserves every CFGR field except the documented prescaler and
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// system-clock-source fields, which are written with encodings valid for F722.
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unsafe {
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write.bits(
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(read.bits() & !((0x0f << 4) | (0x07 << 10) | (0x07 << 13) | 0x03))
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| (0b101 << 10)
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| (0b100 << 13)
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| 0b10,
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)
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}
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});
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if !wait_until(CLOCK_SWITCH_POLL_LIMIT, || rcc.cfgr().read().sws().is_pll()) {
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return Err(ClockProfileError::SystemClockNotPll);
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}
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Ok(())
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}
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fn wait_until(limit: u32, mut ready: impl FnMut() -> bool) -> bool {
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for _ in 0..limit {
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if ready() {
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return true;
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}
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}
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false
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}
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