277 lines
8.8 KiB
Rust
277 lines
8.8 KiB
Rust
//! STM32F722 USART routes used by supported boards.
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use kaptan_log::KaptanError;
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use stm32f7::stm32f722;
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/// UART baud-rate configuration error.
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#[derive(Clone, Copy, Debug, Eq, PartialEq, KaptanError)]
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pub enum BaudRateError {
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/// Zero is not a valid baud rate.
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Zero,
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/// The requested divisor cannot fit USART BRR.
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OutOfRange,
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}
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/// Terminal result from acknowledging a USART receive interrupt.
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#[derive(Clone, Copy, Debug, Eq, PartialEq)]
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pub enum ReceiveInterrupt {
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/// One received byte was removed from the UART data register.
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Byte(u8),
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/// A serial transport fault invalidated the current receive stream.
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Fault,
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/// This USART interrupt did not have a receive event pending.
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NotPending,
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}
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/// Owns configured full-duplex USART1 hardware.
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///
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/// The family platform owns schematic-selected pin setup. Configure pins
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/// before constructing this type.
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pub struct Usart1Tx {
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peripheral: stm32f722::USART1,
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}
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/// Owns configured full-duplex USART2 hardware.
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///
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/// The family platform owns schematic-selected pin setup. Configure pins
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/// before constructing this type.
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pub struct Usart2Tx {
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peripheral: stm32f722::USART2,
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}
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impl Usart2Tx {
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/// Enables USART2 and configures 8N1 transmit and receive operation.
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pub fn new(
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rcc: &stm32f722::RCC,
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peripheral: stm32f722::USART2,
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peripheral_clock_hz: u32,
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baud: u32,
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) -> Result<Self, BaudRateError> {
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let brr = calculate_brr(peripheral_clock_hz, baud)?;
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// Do not inherit a bootloader's USART2 kernel-clock selection. The
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// F722 flight clock profile supplies `peripheral_clock_hz` from PCLK1,
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// so select PCLK1 before programming BRR.
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rcc.dckcfgr2().modify(|_, write| write.usart2sel().apb1());
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rcc.apb1rstr()
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.modify(|_, write| write.usart2rst().set_bit());
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rcc.apb1rstr()
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.modify(|_, write| write.usart2rst().clear_bit());
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rcc.apb1enr().modify(|_, write| write.usart2en().set_bit());
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peripheral.brr().write(|write| {
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// SAFETY: `brr` is validated to fit the complete BRR register.
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unsafe { write.bits(u32::from(brr)) }
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});
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peripheral.cr1().write(|write| {
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write
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.te()
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.set_bit()
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.re()
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.set_bit()
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.rxneie()
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.set_bit()
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.ue()
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.set_bit()
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});
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peripheral.cr2().write(|write| write.stop().stop1());
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Ok(Self { peripheral })
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}
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pub(crate) fn enable_dma_transmit(&self) {
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self.peripheral.cr3().write(|write| write.dmat().set_bit());
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}
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pub(crate) fn transmit_data_register_address(&self) -> u32 {
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self.peripheral.tdr().as_ptr() as u32
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}
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/// Acknowledges one USART2 receive interrupt without accessing TX state.
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pub fn acknowledge_receive_interrupt() -> ReceiveInterrupt {
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// SAFETY: the platform binds USART2 exactly once and this function touches
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// only its receive/error registers, never the TX DMA configuration.
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let peripheral = unsafe { &*stm32f722::USART2::ptr() };
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acknowledge_receive_interrupt(peripheral)
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}
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}
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impl Usart1Tx {
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/// Enables USART1 and configures 8N1 transmit and receive operation.
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pub fn new(
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rcc: &stm32f722::RCC,
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peripheral: stm32f722::USART1,
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peripheral_clock_hz: u32,
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baud: u32,
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) -> Result<Self, BaudRateError> {
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let brr = calculate_brr(peripheral_clock_hz, baud)?;
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// Do not inherit a bootloader or earlier image's USART1 kernel-clock
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// selection. The F722 platform passes PCLK2 when calculating BRR, so
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// select it explicitly before programming the divisor.
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rcc.dckcfgr2().modify(|_, write| write.usart1sel().apb2());
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rcc.apb2rstr()
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.modify(|_, write| write.usart1rst().set_bit());
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rcc.apb2rstr()
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.modify(|_, write| write.usart1rst().clear_bit());
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rcc.apb2enr().modify(|_, write| write.usart1en().set_bit());
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peripheral.brr().write(|write| {
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// SAFETY: `brr` is validated to fit the complete BRR register.
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unsafe { write.bits(u32::from(brr)) }
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});
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peripheral.cr1().write(|write| {
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write
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.te()
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.set_bit()
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.re()
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.set_bit()
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.rxneie()
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.set_bit()
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.ue()
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.set_bit()
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});
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peripheral.cr2().write(|write| write.stop().stop1());
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Ok(Self { peripheral })
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}
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pub(crate) fn enable_dma_transmit(&self) {
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self.peripheral.cr3().write(|write| write.dmat().set_bit());
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}
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pub(crate) fn transmit_data_register_address(&self) -> u32 {
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self.peripheral.tdr().as_ptr() as u32
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}
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/// Acknowledges one USART1 receive interrupt without accessing TX state.
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///
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/// The platform invokes this only from the `USART1` interrupt. USART1 TX DMA
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/// owns its disjoint data register and DMA stream, so this static route may
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/// safely acknowledge RX while that transfer is active.
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pub fn acknowledge_receive_interrupt() -> ReceiveInterrupt {
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// SAFETY: the platform binds USART1 exactly once and this function touches
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// only its receive/error registers, never the TX DMA configuration.
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let peripheral = unsafe { &*stm32f722::USART1::ptr() };
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acknowledge_receive_interrupt(peripheral)
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}
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}
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/// Owns configured UART4 hardware.
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///
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/// This route is intended for peripherals that continuously stream data, such
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/// as the MTF-01. It does not enable DMA state.
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pub struct Uart4 {
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_peripheral: stm32f722::UART4,
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}
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impl Uart4 {
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/// Enables UART4 and configures 8N1 transmit and receive operation.
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pub fn new(
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rcc: &stm32f722::RCC,
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peripheral: stm32f722::UART4,
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peripheral_clock_hz: u32,
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baud: u32,
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) -> Result<Self, BaudRateError> {
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let brr = calculate_brr(peripheral_clock_hz, baud)?;
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rcc.apb1rstr().modify(|_, write| write.uart4rst().set_bit());
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rcc.apb1rstr()
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.modify(|_, write| write.uart4rst().clear_bit());
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rcc.apb1enr().modify(|_, write| write.uart4en().set_bit());
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peripheral.brr().write(|write| {
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// SAFETY: `brr` is validated to fit the complete BRR register.
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unsafe { write.bits(u32::from(brr)) }
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});
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peripheral.cr1().write(|write| {
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write
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.te()
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.set_bit()
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.re()
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.set_bit()
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.rxneie()
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.set_bit()
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.ue()
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.set_bit()
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});
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peripheral.cr2().write(|write| write.stop().stop1());
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Ok(Self {
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_peripheral: peripheral,
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})
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}
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/// Acknowledges one UART4 receive interrupt.
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pub fn acknowledge_receive_interrupt() -> ReceiveInterrupt {
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// SAFETY: the platform binds UART4 exactly once and this function
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// accesses only its receive and error registers.
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let peripheral = unsafe { &*stm32f722::UART4::ptr() };
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acknowledge_receive_interrupt(peripheral)
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}
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}
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fn acknowledge_receive_interrupt(
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peripheral: &stm32f722::usart1::RegisterBlock,
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) -> ReceiveInterrupt {
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let status = peripheral.isr().read();
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let fault = status.pe().is_error()
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|| status.fe().is_error()
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|| status.nf().is_noise()
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|| status.ore().is_overrun();
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if status.rxne().is_data_ready() {
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let byte = peripheral.rdr().read().rdr().bits() as u8;
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if fault {
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clear_receive_errors(peripheral);
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ReceiveInterrupt::Fault
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} else {
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ReceiveInterrupt::Byte(byte)
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}
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} else if fault {
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clear_receive_errors(peripheral);
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ReceiveInterrupt::Fault
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} else {
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ReceiveInterrupt::NotPending
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}
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}
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fn clear_receive_errors(peripheral: &stm32f722::usart1::RegisterBlock) {
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peripheral.icr().write(|write| {
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write
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.pecf()
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.clear()
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.fecf()
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.clear()
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.ncf()
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.clear()
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.orecf()
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.clear()
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});
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}
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const fn calculate_brr(peripheral_clock_hz: u32, baud: u32) -> Result<u16, BaudRateError> {
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if baud == 0 {
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return Err(BaudRateError::Zero);
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}
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let divisor = (peripheral_clock_hz + (baud / 2)) / baud;
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if divisor == 0 || divisor > u16::MAX as u32 {
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Err(BaudRateError::OutOfRange)
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} else {
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Ok(divisor as u16)
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}
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}
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#[cfg(test)]
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mod tests {
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use super::{BaudRateError, calculate_brr};
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#[test]
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fn calculates_reset_clock_brr() {
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assert_eq!(calculate_brr(16_000_000, 115_200), Ok(139));
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}
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#[test]
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fn rejects_zero_baud() {
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assert_eq!(calculate_brr(16_000_000, 0), Err(BaudRateError::Zero));
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}
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}
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