libs/kaptan-stm32f7: add clock GPIO and timer drivers

libs/kaptan-stm32f7/src/stm32f722/tim2.rs

@@ -0,0 +1,53 @@
+//! STM32F722 TIM2 periodic interrupt configuration.
+
+use stm32f7::stm32f722;
+
+/// Precomputed TIM2 periodic-update configuration.
+#[derive(Clone, Copy, Debug, Eq, PartialEq)]
+pub struct Tim2PeriodicConfig {
+    /// Timer prescaler register value.
+    pub prescaler: u16,
+    /// Timer auto-reload register value.
+    pub auto_reload: u32,
+}
+
+/// TIM2 configured to issue periodic update interrupts.
+pub struct Tim2Periodic {
+    peripheral: stm32f722::TIM2,
+}
+
+impl Tim2Periodic {
+    /// Enables TIM2 with the supplied board-derived period configuration.
+    pub fn new(
+        rcc: &stm32f722::RCC,
+        peripheral: stm32f722::TIM2,
+        config: Tim2PeriodicConfig,
+    ) -> Self {
+        rcc.apb1rstr().modify(|_, write| write.tim2rst().set_bit());
+        rcc.apb1rstr()
+            .modify(|_, write| write.tim2rst().clear_bit());
+        rcc.apb1enr().modify(|_, write| write.tim2en().set_bit());
+        peripheral.cr1().modify(|_, write| write.cen().clear_bit());
+        peripheral.psc().write(|write| {
+            // SAFETY: `prescaler` is exactly the 16-bit PSC register width.
+            unsafe { write.psc().bits(config.prescaler) }
+        });
+        peripheral.arr().write(|write| {
+            // SAFETY: TIM2 ARR is a 32-bit register and accepts `auto_reload`.
+            unsafe { write.arr().bits(config.auto_reload) }
+        });
+        peripheral.egr().write(|write| write.ug().set_bit());
+        peripheral.sr().modify(|_, write| write.uif().clear_bit());
+        peripheral.dier().modify(|_, write| write.uie().set_bit());
+        peripheral.cr1().modify(|_, write| write.cen().set_bit());
+
+        Self { peripheral }
+    }
+
+    /// Acknowledges a TIM2 update interrupt.
+    pub fn acknowledge_update(&mut self) {
+        self.peripheral
+            .sr()
+            .modify(|_, write| write.uif().clear_bit());
+    }
+}