platforms/stm32f7: keep USART2 DMA requests enabled
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@@ -27,6 +27,7 @@ impl Usart2TxDma {
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/// Enables DMA1 and connects USART2 TX to its fixed request route.
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/// Enables DMA1 and connects USART2 TX to its fixed request route.
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pub fn new(rcc: &stm32f722::RCC, usart: Usart2Tx) -> Self {
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pub fn new(rcc: &stm32f722::RCC, usart: Usart2Tx) -> Self {
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rcc.ahb1enr().modify(|_, write| write.dma1en().set_bit());
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rcc.ahb1enr().modify(|_, write| write.dma1en().set_bit());
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usart.enable_dma_transmit();
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Self { usart }
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Self { usart }
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}
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}
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@@ -44,12 +45,8 @@ impl Usart2TxDma {
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}
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}
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self.clear_interrupt_flags();
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self.clear_interrupt_flags();
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// Idle USART2 has TXE set. Enabling DMAT *after* the stream is armed
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// creates the initial request for byte zero without manually writing
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// TDR, so the whole frame is owned by DMA.
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self.configure_stream(bytes);
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self.configure_stream(bytes);
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self.stream().cr().modify(|_, write| write.en().enabled());
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self.stream().cr().modify(|_, write| write.en().enabled());
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self.usart.enable_dma_transmit();
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Ok(())
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Ok(())
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}
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}
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@@ -73,14 +70,6 @@ impl Usart2TxDma {
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.st(6)
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.st(6)
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.cr()
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.cr()
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.modify(|_, write| write.en().disabled());
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.modify(|_, write| write.en().disabled());
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// SAFETY: USART2 is initialized once by `Usart2Tx::new`; this ISR
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// clears only its DMA transmit-request enable after the stream's
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// terminal status has been observed.
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unsafe {
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(&*stm32f722::USART2::ptr())
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.cr3()
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.modify(|_, write| write.dmat().clear_bit())
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};
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controller.hifcr().write(|write| {
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controller.hifcr().write(|write| {
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write
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write
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.ctcif6()
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.ctcif6()
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